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Learn OVM/UVM

Published on Feb 09, 2016

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1.

Learn OVM/UVM

SystemVerilog based Methodology
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2.

What is OVM/UVM

  • Popular Verification Methodologies
  • SystemVerilog Language based 
  • Aimed at improving Verification productivity
  • Must have skills for a Verification job in VLSI
  • Hard to learn from text books or user guides
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3.

Learn OVM/UVM from Scratch

Self paced online courses
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Ramdas Mozhikunnath M

https://www.facebook.com/ramdasmozhikunnath.m